Process control is very important in the fabrication of ultra-large scale integrated circuits. Through a series of deposition, doping, photolithography and etch steps, the starting substrate and subsequent layers are converted into integrated circuits, with a single substrate producing from tens to thousands or even millions of integrated devices, depending on the size of the wafer and the complexity of the circuits.
One area in which process control is particularly critical is the fabrication of transistor gate dielectrics. In the pursuit of ever faster and more efficient circuits, semiconductor designs are continually scaled down with each product generation. Transistor switching time plays a large role in the pursuit of faster circuit operation. Switching time, in turn, can be reduced by reducing the channel length of the transistors. In order to realize maximum improvements in transistor performance, vertical dimensions should be scaled along with horizontal dimensions. Accordingly, effective gate dielectric thickness, junction depth, etc. will all decrease with future generation integrated circuits.
High quality, thin dielectric layers are also desirable for memory cell capacitors. Integrated capacitors in memory arrays must exhibit a certain minimum capacitance for proper data storage and retrieval. As the chip area or “footprint” available per memory cell shrinks with each progressive generation of integrated circuits, the required capacitance per unit of footprint has increased. Many complex folding structures have been proposed for increasing capacitance through increased capacitor electrode surface area for a given cell footprint. Often, these structures require extremely complex fabrication steps, increasing the cost of processing significantly. Accordingly, other efforts to increase capacitance for a given memory cell space have focused on the capacitor dielectric, since reducing the thickness of the dielectric also increases overall capacitance.
Conventional thin dielectrics are formed of high quality silicon dioxide, also referred to herein as “silicon oxide.” Ultra-thin silicon oxide layers (e.g., less than 5 nm), however, have been found to exhibit high defect densities, including pinholes, charge trapping states and, in transistor applications, susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology. Moreover, even if the integrity of the silicon oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of silicon oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling and largely determines silicon oxide scaling limits. For example, in transistor gate dielectrics, these scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., “Thin Gate Oxides Promise High Reliability,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215-222.
Theoretically, incorporating materials of higher dielectric constant into the dielectric opens the door to further device scaling. Higher dielectric constants (k) allow materials currently under investigation to exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness (EOT) can be achieved without tunnel-limited behavior.
Silicon nitride has been investigated for its higher k value and diffusion barrier properties. However, silicon nitride has been found to exhibit a higher density of defects, such as interface trapping states, as compared to oxides. One solution to the individual shortcomings of oxides and nitrides is to produce a hybrid layer. Incorporating nitrogen into silicon oxide, to form silicon oxynitride, provides improved gate dielectrics. See, e.g., Leonarduzzi & Kwong, “improving Performance with Oxynitride Gate Dielectrics,” SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 225-230. Similarly, forming silicon nitride over thin silicon oxide layers, has been found to reduce defect densities while considerably lowering overall gate dielectric equivalent oxide thickness. See, e.g., Kim et al., “Ultra Thin (<3 nm) High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In-Situ Rapid Thermal Processing,” IEDM 97 (1997), pp. 463-466. The benefits of gate dielectrics made from silicon nitride are limited, however, because of the marginal increase in dielectric constant afforded by silicon nitride, particularly when used in conjunction with silicon oxide.
Accordingly, other efforts to increase capacitance have focused on materials with significantly higher dielectric constants (high-k materials). Certain metal oxides, such as barium strontium titanate (BST), strontium bismuth tantalate (SBT), hafnium oxide (HfO2), zirconium oxide (ZrO2) tantalum oxide (Ta2O5), etc., exhibit high relative permittivity (dielectric constant or k values) and are thus promising for fabricating gate dielectrics with increased capacitances. Several factors have limited the integration of such materials into current process flows, including the relative instability of high-k materials, a tendency to exhibit high defect densities, leakage currents, and the difficulty of avoiding oxidation of surrounding materials during high-k dielectric deposition and annealing.
To avoid problems with oxidation of surrounding materials, known techniques have focused on extremely complex integration techniques, the use of noble, non-oxidizing, or conductive oxide materials for electrodes and diffusion barriers in the process sequence. For example, such techniques are disclosed in U.S. Pat. No. 5,392,189; U.S. Pat. No. 5,619,393; U.S. Pat. No. 5,633,781; and U.S. Pat. No. 6,265,740 B1. Amorphous dielectric materials can decrease the leakage current, but the effective thickness of the insulating layer increases due to lower dielectric constants amorphous materials. Other references disclose the use of amorphous materials between grains of higher dielectric constant crystals. See, e.g., U.S. Pat. No. 4,464,701; U.S. Pat. No. 6,014,610; and U.S. Pat. No. 5,617,290. Relatively complex process flows, however, are required to achieve such structures, and the overall dielectric constant of multiple-layer dielectric structures dilutes the effect of the high-k materials.
A need exists, therefore, for more effective methods of forming high quality dielectric layers.